Tap cells are commonly used in the integrated circuit design. Tap cells provide the body bias of the transistors and have the function of preventing the undesirable latch-up of integrated circuits, which latch-up is resulted from parasitic bipolar transistors of integrated circuits. Through the tap cells, n-well regions are coupled to VDD power rails, and p-well regions or p-type substrates are coupled to VSS power rails, which are electrical ground. Coupling the well regions and substrate regions to the VDD power rails and VSS power rails, respectively, may result in a reduction in the substrate resistance, and the reduction in the undesirable positive feedback in the integrated circuit.
For process uniformity and device performance reasons, dummy gate electrodes (dummy polysilicon lines) were added in the tap cells. This causes the adverse increase in the chip area usage of the tap cells. Since the tap cells need to be placed with appropriate distances from each other, an integrated circuit may include many tap cells. The chip-area penalty caused by the dummy gate electrodes is thus high.